Extensive research is now underway in the field of traffic monitoring systems, particularly focusing on the automated detection of traffic accidents. Surveillance cameras that are connected to traffic control systems are being installed at a growing number of urban intersections. Computer vision approaches have the potential to be very valuable tools for automatically detecting accidents. This study aims to provide an innovative and efficient framework for traffic monitoring applications, specifically focusing on detecting accidents occurring at crossings. The proposed framework starts with the first hierarchical phase, which involves the use of a Kalman filter and the Hungarian algorithm for object tracking and association. The second phase is referred to as trajectory conflict analysis, the third step is known as the advanced YOLOv4 technique, and the final stage is named efficient and accurate object detection. Subsequently, the procedure is completed. During the object tracking stage, the presence of obstructions, overlapping objects, and changes in shape are all carefully considered. This is achieved by using a distinct cost function. Analyzing object trajectories involves considering characteristics such as speed, angle, and distance in order to identify various forms of trajectory conflicts. Examples of these disputes include those pertaining to autos, individuals, and bicycles. These examples represent just a small fraction of the many forms of trajectory conflicts that may be detected. The experiment's results, based on video footage obtained from genuine traffic scenarios, indicate that the recommended approach has potential for use in real-time traffic monitoring technologies. The tests include evaluating various lighting conditions and video sequences that are imported from YouTube

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This paper considers the security problem of outsourcing storage from user devices to the cloud. A secure searchable encryption scheme is presented to enable searching of encrypted user data in the cloud. The scheme simultaneously supports fuzzy keyword searching and matched results ranking, which are two important factors in facilitating practical searchable encryption. A chaotic fuzzy transformation method is proposed to support secure fuzzy keyword indexing, storage and query. A secure posting list is also created to rank the matched results while maintaining the privacy and confidentiality of the user data, and saving the resources of the user mobile devices. Comprehensive tests have been performed and the experimental results show that the proposed scheme is efficient and suitable for a secure searchable cloud storage system.

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Communication between devices, also known as device-to-device (D2D) communications, should have characteristics such as high energy and spectrum economy, enormous system capacities, and very quick data rates. A great deal of research on device-to-device communication (D2D) was carried out as a consequence of these speed gains; nevertheless, they also brought to light critical problems that need to be resolved before they can be used to their full potential in 5G networks. D2D transmission has the potential to increase the performance of 5G networks in a variety of ways, including the total capacity of the system, the data throughput, the energy efficiency, and the spectrum economy. This is the most significant obstacle that the 5G network must overcome in order to fulfill the requirements of high speed, low latency, and heavy traffic. In addition to the aforementioned requirements, the cellular networks of the future will also need to have improved speed, decreased power consumption, and quality of service. However, despite this, there are a number of serious problems that are linked with this choice. Improved D2D communication (DLID2DC) is the name given to a system that has been presented to overcome these challenges and improve D2D networks. This solution is based on deep learning methodology. The suggested model does away with automation in favor of a strategy that investigates the needs for public cloud communication by using explainable artificial intelligence (XAI). This is done in order to support 5G networks. For the purpose of delivering machine data from a distant server to mobile devices, there are a variety of ways available, each of which is adapted to particular needs. The model ensures that the available radio resources are used in the most efficient manner possible for direct-to-device (D2D) transmission by using deep learning methods. According to the results of the studies, the DLID2DC approach is superior to its rivals in terms of speed, fairness, end-to-end latency, and energy efficiency.

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The purpose of this study is to present a low-power approximation multiplier that is not only rapidly effective but also efficient. Rounding the operands to the closest two-exponential number is achieved by the use of this approach. Due to the reduction in the computationally expensive section of the multiplication, this results in an improvement in speed and energy usage. However, this comes at the expense of a little fall in accuracy. It is possible to handle signed as well as unsigned multiplications by using the technique that has been presented. There are three different hardware implementations of the approximative multiplier that we supply. These implementations provide signed and unsigned operations, respectively. The performance of the suggested multiplier is assessed using certain design criteria, and it is compared to the performance of comparable approximative and accurate multipliers. Furthermore, we investigated the performance of the suggested approximation multiplier in two different image processing applications, namely sharpening and smoothing operations.

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Distributed arithmetic (DA) calculation is generally utilized for FIR channel execution. In the starting, DA was proposed as successive DA (SDA), and at that point was stretched out to parallel DA (PDA) for higher throughput. This project introduces a novel PDA FIR channel design in view of 4:2 compressors which can be mapped on Xilinx FPGAs effectively. Overall, our proposed FIR models accomplish 17.5% decrease in asset use and 20.7% change in execution contrasted with the cutting edge PDA FIR channel. Additionally, overall, there is 57.9% decrease in asset utilization and 23.0% change in execution contrasted with PDA FIR. Another 4:2 compressor design in light of changing some inward conditions are proposed. Furthermore, utilizing an efficient full-snake (FA) square is considered to have a fast blower. Three 4:2 compressors are considered for examination. The proposed engineering is contrasted and the best existing plans exhibited in the best in class writing regarding force, deferral and territory. The project presents compressors that are broadly utilized as building squares of multipliers.

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Power analysis (PA) attacks have emerged as a serious threat to security systems since they allow for the extraction of confidential data. These attacks are carried out by analyzing the current that is consumed by the system's power supply. Embedded memories are an essential component of these systems. These memories are typically constructed using six-transistor (6T) static random-access memory (SRAM) cells at the time of implementation. Because of the connection between the current characteristics and the data that has been written, conventional SRAM cells are susceptible to attacks that include side-channel power analysis. The 7T SRAM cell that we have presented is intended to be more secure and resistant to assaults of this kind.  it utilizes a two-phase write operation and has an additional transistor in comparison to the 6T SRAM version, the data that is stored is much less connected with the amount of power that is used during write operations. The proposed 7T SRAM cell, when constructed utilizing a 28 nm technology, demonstrates a write energy standard deviation between write '1' and '0' operations that is more than a thousand times lower than that of a conventional 6T SRAM as compared to the energy standard deviation. The recommended cell has a shorter write latency of 19% to 38% and a lower write energy of 39% to 53% when compared to current power analysis resistant SRAM cells. Additionally, the suggested cell has a lower write energy of 39% to 53%.

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A Bose-Chaudhuri-Hocquenghem (BCH) code decoder that is both highly efficient and consumes very little power when decoding is shown in this paper. DEC-TED is an abbreviation that stands for "double-error-correcting and triple error-detecting." It is an excellent decoder for use in constructing memory to repair mistakes since it is both very efficient and very power efficient. The purpose of our proposal is to develop an adaptive error correcting strategy with the intention of making the process of decoding the DEC-TED BCH code more effective. Immediately after the establishment of a syndrome, this method counts the amount of errors that are present in a codeword and then applies a different error correction algorithm based on the specific error conditions. By increasing the efficiency of the decoding process, the adaptive error correction approach brings about a considerable reduction in both the power consumption and the average decoding delay.  further reduce power consumption, we suggest a method called invalid-transition-inhibition. This approach eliminates invalid transitions that are brought about by syndrome vector errors in the error-finding block. The suggested decoders for the (79, 64, 6) BCH code lower power consumption by approximately 70 percent when compared to the traditional completely parallel decoder that operates at a raw bit-error rate of 104-102. These findings were obtained by synthesis utilizing a technology library that is consistent with industry requirements and uses a 65-nm technology.

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