| S.No | Title | Author | Description | Download | |
|---|---|---|---|---|---|
| 1 | Method Of Eliminating Harmonics In Cascaded H-Bridge Multilevel Inverters | 1.Bojja Swetha ,2.M Ragini , 3.Dr T Kranthi Kumar |
Because of their straightforward construction and the ease with which they may be used, cascaded structured multilevel inverters are becoming more significant in the field of electrical engineering. For the purpose of this inquiry, the most efficient approach for picking and removing harmonics from a nine-level inverter is used in order to dampen a specific lower-order harmonic, which ultimately results in a reduction in the total harmonic distortion of the inverter. An strategy known as Newton-Raphson is used in order to achieve the goal of discovering the switching angles that are responsible for the reduction of certain lower order harmonics. The third, fifth, and seventh harmonics are the ones that are removed when the harmonics are eliminated in that exact sequence. A simulation of a nine-level inverter was carried out in SIMULINK, and all of the findings of that simulation are shown across this page. There are a number of keywords that might be utilised, including nine-level multi-level inverter, modular inverter, and control of the inverter |
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| 2 | A Three-Operand Binary Adder Using An Advanced VLSI Architecture Fast And Area-Efficient | 1.Daram Praveen , 2.Dr S Kishore Reddy , 3.Dr K. Sanjeeva Rao , 4.Vasantha Naga Raju, 5.G.srinivas |
A three-operand binary adder is used to execute modular arithmetic in a number of cryptography and pseudorandom bit generator (PRBG) methods. Most of the time, the carry save adder (CS3A) is utilised to execute three-operand addition. The ripple-carrying stage (n) in the CS3A adds a transmission delay of O. The critical route time can be lowered down by employing a parallel prefix two-operand adder, such as the Han-Carlson (HCA) method for three-operand addition. The three-operand binary addition operation is done with a revolutionary adder architecture that is both quick and takes up little space. The adder delay is reduced to O(log2 n) using this solution, which is a relatively modest amount given the complexity of the problem. This is accomplished by the utilisation of pre-compute bitwise addition, which is then followed by carry prefix calculation logic. The design that was suggested was developed using a 32nm CMOS technology source that is not difficult to locate. Additionally, it has been validated to ensure that it is compatible with an FPGA device. Following the completion of post-synthesis, the recommended adder performed 3.12, 5.31, and 9.28 times better than the CS3A for designs with 32 bits, 64 bits, and 128 bits respectively. When it comes to processing huge amounts of data in a short amount of time, the HC3B is superior to the adder due to the fact that it requires less space, consumes less power, and has a shorter delay. When it comes to peak delay power (PDP) and average delay power (ADP), the adder that was recommended performs far better than the three-operand adder approaches that are currently in use. This is something that should be mentioned |